Simultaneous recording of neuropotentials over a large number of electrodes from the brain provides an effective way for neuroscientists and clinicians to study the brain state dynamics and understand the nature of various neurophysiological behaviors. It has a wide range of applications, including the development of brain controlled neural prostheses, which are controlled directly by thoughts. Recent clinical trials with paralyzed human volunteers have shown that it is possible to restore limb movement by such kind of neuroprosthetic devices. This calls for the development of low-power low-voltage implantable multi-channel neural recording interface integrated circuit (IC).
Effective and reliable neural research and diagnosis rely on multi-channel recordings. High density recording channels from 100 to as high as 256 are possible. On the other hand, a recording microsystem implanted in the brain requires extremely rigid requirement on power consumption of the high density recording electronics, as slightly higher heat dissipation will induce damage to the surrounding tissue, thus making the device not suitable for long term monitoring. In addition, the power of implantable devices is usually provided either by battery or through wireless power link. In order to avoid frequent replacement of battery or excessive electromagnetic wave exposure to live subjects, low power consumption is especially critical. Meanwhile, chip area is also a key constraint for implantable device to minimize the surgical damage. Therefore, the requirements of ultra low power consumption, minimum chip area and high density recording provide a great challenge to IC designers.
Conventional multi-channel biomedical recording sensor interface IC requires signal conditioning and digitization blocks, which are usually realized by low-noise preamplifier and analog-to-digital converter (ADC). Successive approximation ADC (SAR ADC) is widely adopted in biomedical recording system due to its low power, high resolution and moderate speed. Due to chip area restraint, one ADC is usually shared by multiple analog front-end recording channels by employing an n-to-1 multiplexer as shown in FIG. 1A to be described later, where n is the number of channels sharing one ADC. In order to preserve the sampling frequency for each channel, the sampling frequency of the ADC needs to be increased to n times of the sampling frequency for one channel mode. As there is only one sample and hold (S/H) circuit in the system, all activities of the ADC take place in series. Increasing the sampling frequency means a shorter time for tracking and conversion, which are two essential actions for the SAR ADC. Therefore, a much higher driving capability buffer is required to maintain the tracking error within an acceptable range due to the shorter tracking time. As a result, the power consumption of the overall system will increase, which is not desirable for implantable devices.
Efforts have been made in designs to reduce the power consumption of individual functional block, such as the low-noise preamplifier and the ADC, which can be realized with few μW power consumption. However, little has been done in optimizing the overall system power consumption. Due to the shortened tracking time of the conventional multi-channel system architecture, an associated preceding buffer of the ADC can draw tens of μW power, thereby overriding any reduction in the power of the preamplifier and the ADC, and resulting in a high total power consumption of the system.
In order to maintain low enough power consumption, some conventional designs adopt data compression or spike detection algorithm to minimize the power consumption. However, this approach may lose some useful information and lead to inaccurate outcome. Therefore, complete and raw neural data are preferred for neural activity analysis and diagnosis. As a result, an ADC with at least 8-bit resolution is necessary in a neural recording system.
An alternative approach to reduce the system power is to implement one sample and hold (S/H) circuit for each analog recording channel, as shown in FIG. 2A to be described later. By doing so, the tracking time of the ADC is extended to maximum and the power consumption of the buffer is minimized. However, the area of one S/H circuit is almost equal to the ADC area. Therefore, employing one S/H circuit per channel will significantly increase the area of the overall system.
In order to reduce the chip area of a biomedical recording IC, multi-channel analog signals are usually multiplexed to share one ADC, as shown in FIG. 1A. FIG. 1A shows a schematic diagram of a conventional multiplexed multi-channel recording system 100. The conventional recording system 100 includes a plurality of buffers 102a, 102b, 102c, each providing an analog input 103a, 103b, 103c, corresponding to respective analog channels, to a multiplexer 104. The recording system 100 further includes a single sample and hold (S/H) circuit 106 coupled in series with the multiplexer (MUX) 104, and providing an output signal to the analog to digital converter (ADC) (e.g. SAR ADC) 108. The S/H circuit 106 may be within the ADC 108. While three buffers 102a, 102b, 102c, and three analog inputs 103a, 103b, 103c are shown, there may be n number of buffers providing n number of analog inputs (e.g. n may be 10).
For the recording system 100, the n-channel (multi-channel) analog inputs (e.g. 103a, 103b, 103c) occupy the ADC 108 in time sharing basis. For example, if the input analog signal is within the bandwidth of fsignal, the sampling frequency of the ADC 108 is at least (2nfsignal) according to the Nyquist rate, and the ADC 108 allocates a time period of TADC=1/(2nfsignal) to each analog channel of the respective analog inputs 103a, 103b, 103c, through the n-bit control signal of the multiplexer 104. Before digitization by the ADC 108 takes place, the S/H circuit 106 needs to track or sample the analog input voltage level and stores it in a sampling capacitor of the S/H circuit 106. The tracking (or sampling) process occupies a time partially of the TADC. For a conventional SAR ADC, the tracking/sampling period, Tsample, is 1/(N+1) of TADC, and the conversion (or holding) period Tconv is [N/(N+1)] of TADC for a N-bit ADC, where N is the number of bits of the ADC 108.
FIG. 1B shows a schematic diagram of a timing diagram 120 for the recording system 100 of FIG. 1A, illustrating the time sharing scheme of the recording system 100. The time interval indicated by ‘S’ represents the sampling period and the respective time intervals indicated by ‘H1’, ‘H2’, . . . , ‘Hn’ represent the conversion periods of the S/H circuit 106 and the ADC 108. Using channel 1, Ch1, corresponding to an analog input, as a non-limiting example, the block ‘S’ 122a and the block ‘H1’ 122b respectively represent the sampling period, with a time interval of TADC/(N+1), and the conversion period, with a time interval of [TADCN/(N+1)], related to Ch1. The cycle time or period between successive same channels is 1/(2fsignal). It should be appreciated that the various time intervals/durations are for illustration purposes and not drawn to scale.
During the sampling period of one analog input channel, e.g. Ch1, Ch2, Ch3, or one analog input 103a, 103b, 103c, the multiplexer 104 connects the buffer output of this channel with the S/H capacitor of the S/H circuit 106 or the ADC 108, such that the buffer (e.g. 102a, 102b, 102c) will charge or discharge the S/H capacitor, and the current output voltage level of the buffer (e.g. 102a, 102b, 102c) will be stored in the S/H capacitor. The required output current of the buffer (e.g. 102a, 102b, 102c), Ibuffer, can be expressed by the following equation:
                                          I            buffer                    =                                                                      C                  s                                ×                Δ                ⁢                                                                  ⁢                V                                            T                sample                                      =                          2              ⁢              n              ⁢                                                          ⁢                                                f                  signal                                ⁡                                  (                                      N                    +                    1                                    )                                            ⁢                              C                s                            ⁢              Δ              ⁢                                                          ⁢              V                                      ,                            (                  Equation          ⁢                                          ⁢          1                )            where Cs is the sampling capacitance of the S/H capacitor of the ADC 108 and ΔV is the voltage difference between the buffer output of the current channel and the previous channel at the time when sampling/tracking of the current channel starts, Tsample is the sampling period, n is the number of analog inputs (e.g. 103a, 103b, 103c) or input channels, fsignal is the bandwidth of an input analog signal (e.g. 103a, 103b, 103c) and N is the number of bits of the ADC 108.
In addition, the bandwidth of the buffer (e.g. 102a, 102b, 102c), fbuffer, needs to fulfill the following equations in order to maintain the tracking error within half least significant bit (LSB) of the ADC 108:
                                          Δ            ⁢                                                  ⁢            V            ×                          [                              e                ^                                  (                                                            -                                              T                                                  sample                          ⁢                                                                                                                                                                      ×                    2                    ⁢                    π                    ⁢                                                                                  ⁢                                          f                      buffer                                                        )                                            ]                                ≤                                    1              2                        ×                                          V                pp                                            2                N                                                    ,                            (                  Equation          ⁢                                          ⁢          2                )            where ‘^’ represents a power operation, e.g. e^5=e5. Therefore, by re-arranging Equation 2, Equations 3 and 4 below may be obtained;
                                          f            buffer                    ≥                                    1                              2                ⁢                π                ⁢                                                                  ⁢                                  T                  sample                                                      ⁢                          ln              (                                                                    2                                          N                      +                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                  V                                                  V                  pp                                            )                                      ,                            (                  Equation          ⁢                                          ⁢          3                )            and,
                                          f            buffer                    ≥                                                    n                ⁢                                                                  ⁢                                                      f                    signal                                    ⁡                                      (                                          N                      +                      1                                        )                                                              π                        ⁢                          ln              (                                                                    2                                          N                      +                      1                                                        ⁢                  Δ                  ⁢                                                                          ⁢                  V                                                  V                  pp                                            )                                      ,                            (                  Equation          ⁢                                          ⁢          4                )            where VPP is the full-scale input range of the ADC 108.
As can be seen from Equations 1 and 4, both the required output current of the buffer (e.g. 102a, 102b, 102c), Ibuffer, and the bandwidth of the buffer (e.g. 102a, 102b, 102c), fbuffer, are proportional to n(N+1). In other words, the current drawn by each buffer (e.g. 102a, 102b, 102c) is proportional to the resolution (N-bit) of the ADC 108 and the number, n, of channels that the ADC 108 is supporting. In fact, this is an optimistic estimation as the current required to achieve the bandwidth of nfsignal is larger than nI, where I is the current needed to achieve the bandwidth of fsignal, due to the fact that the parasitic capacitances play more and more important roles in high frequency range and therefore more current is needed to compensate for the parasitic capacitances. With the increase of n, the power consumption of the buffer (e.g. 102a, 102b, 102c) will increase significantly, even for a moderate resolution of the ADC 108. For example, using a conventional multiplexed system structure, the buffer may draw a current of 20.3 μA while the preamplifier draws a current of only 2 μA. Therefore, the buffer (e.g. 102a, 102b, 102c) is the dominant power consumer in the recording system 100 and more effort is needed to minimize the buffer current, as well as the total power of the recording system 100. Therefore, the recording system 100 is power inefficient.
One conventional approach used to lower the power consumption of the buffer is employing a dedicated sample and hold (S/H) circuit for each analog input channel, as shown in FIG. 2A. FIG. 2A shows a schematic diagram of a conventional multiplexed multi-channel recording system 200. The recording system 200 includes a plurality of buffers 202a, 202b, 202c, each providing an analog input 203a, 203b, 203c, to a sample and hold (S/H) circuit 206a, 206b, 206c. The analog signals 203a, 203b, 203c are sampled by the respective sample and hold (S/H) circuits 206a, 206b, 206c before being provided to the multiplexer (MUX) 204 and then passed to the analog to digital converter (ADC) 208 for digitization. While three buffers 202a, 202b, 202c, three analog inputs 203a, 203b, 203c and three S/H circuits 206a, 206b, 206c are shown, there may be n number of buffers providing n number of analog inputs and sampled by n number of S/H circuits (e.g. n may be 10).
By adopting such a system structure, the tracking (or sampling) time is extended from TADC/(N+1) (FIGS. 1A and 1B) to (n−1)TADC as shown in FIG. 2B, which leads to a significant reduction of the buffer current according to Equation 1. FIG. 2B shows a schematic diagram of a timing diagram 220 for the recording system 200 of FIG. 2A. As shown in FIG. 2B, the S/H circuit, S/H1 (e.g. 206a), may process the input signal 222a of channel 1, Ch1, while S/H2 (e.g. 206b) may process the input signal 222b of channel 2, Ch2, S/H3 may process the input signal 222c of channel 3, Ch3, and S/Hn may process the input signal 222d of channel n, Chn.
The respective time intervals indicated by ‘S1’, ‘S2’, . . . , ‘Sn’ represent the sampling period and the respective time intervals indicated by ‘H1’, ‘H2’, . . . , ‘Hn’ represents the conversion period of the respective S/H circuit, S/H1, S/Hn, corresponding to the respective channels, Ch1, Chn. Using channel 1, Ch1, corresponding to the analog input 222a, as a non-limiting example, the blocks ‘S1’ 224a and the blocks ‘H1’ 224b respectively represent the sampling period, with a time duration of (n−1) TADC, and the conversion period, with a time interval of TADC, related to Ch1. The cycle time or period between successive conversion actions of each S/H circuit is 1/(2fsignal). It should be appreciated that the various time intervals/durations are for illustration purposes and not drawn to scale.
With the sampling time of the ADC 208 extended to 2TADC or more (e.g. Tsample≧2TADC), the power consumption of the buffer (e.g. 202a, 202b, 202c) is no longer dominant in the system. However, a longer sampling time, of more than 2TADC, has very little further effect on the total system power, and therefore, having one S/H circuit per input channel may not substantially further reduce the total system power.
In addition, such a multi-channel S/H recording system 200 requires n number of S/H capacitors for the n number of S/H circuits (e.g. 206a, 206b, 206c), which is usually in the range of 3 pF to 5 pF for each capacitor to minimize the effect of parasitic capacitance and maintain the digitization error within an acceptable range. For an SAR ADC, the area of the sampling capacitor takes up about half of the total area of the overall ADC. When the number of channels increases (i.e. n increases), the physical area of the system will increase dramatically due to the increased number of sampling capacitors. Therefore, the recording system 200 is area inefficient. As a result, this multi-channel S/H approach of the recording system 200 is not suitable for implantable biomedical devices or applications with limited chip area constraint.